Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits

The main purpose of the method proposed in this article is to reduce number look-up-table (LUT) elements logic circuits sequential devices. devices are represented by models Mealy finite state machines (FSMs). Thesee so-called MPY FSMs based on two methods structural decomposition (the replacement inputs and encoding output collections). idea use types codes for implementing systems partial Boolean functions. Some functions maximum binary codes; other depend extended codes. reduction LUT counts using twofold assignment. makes it possible obtain FPGA-based FSM with four levels. Only one required implement circuit corresponding any function. An example synthesis shown. results conducted experiments show that approach produces LUT-based better area-temporal characteristics than produced such as Auto One-hot Vivado, JEDI, FSMs. Compared FSMs, values improved. On average, improvement 8.98%, but gain reaches 13.65% fairly complex operating frequency slightly improved compared (up 0.64%). For both frequency, increases together growth numbers inputs, outputs states.